A signal in a logic or switching circuit typically assumes one of two voltage levels representing two states or digital values (e.g., one and zero). A level shifter may be coupled between circuits or sections of circuits that operate using different high and low levels, usually determined by the power supply voltages of such circuits or sections. A conventional level shifter typically changes a high-level output voltage (VOH) to a high-level substantially equal to a power supply voltage (Vddhi) of the next successive circuit or section and the low-level output voltage (VOL) remains at ground potential. These level shifters also often suffer Electrical Over Stress (EOS) leading to time dependent device breakdown (TDDB), particularly when implemented in low-voltage core devices.
Some level shifters have been designed to output VOL at a voltage other than ground. One possibility is to provide low output levels VOL at 20% or more of the high level power soppy (Vddhi). These level shifters typically add a bias between the sources of an NMOS pair and ground, to shift the VOL up by using an external bias or an internal bias circuit. Such an external or internal bias circuit provides a constant bias, which can cause an output voltage of the level shifter to be increased. However, due to the bias, the overdrive headroom for the input signals in the low-power-supply side of the level shifter is reduced by the amount of the bias plus a transistor body effect voltage. Consequently, these level shifters fail to function when the sum of the bias and the threshold voltage of the input transistor is close to the low-power-supply voltage. These level shifters also suffer Electrical Over Stress (EOS) issues, particularly when implemented in low-voltage core devices.
An improved level shifter design would be desirable in the art.